General Integrated Circuit (IC) manufacturing technologies include designing a circuit layout as needed, making masks according to the circuit layout, and performing a series of processes including deposition, exposure, etching and annealing by using the masks in order, thereby manufacturing multiple dies arranged on a wafer at the same time. In multi-die products, dies have respective application scenarios and semiconductor structures, therefore their corresponding circuit patterns are different from one another, which may lead to notable non-uniformity of circuit patterns across the effective field of the wafer.
For example, a Radio Frequency (RF) circuit die has a low distributing density of Active Areas (AAs) and a low distributing density of gates, and an embedded memory circuit die has a high distributing density of AAs and a high distributing density of gates. On the other hand, a single die may have regions with different distributing densities of AAs or gates. The difference between distributing densities of semiconductor structures such as AAs and gates may result in a difference between local temperatures of the wafer during Rapid Thermal Annealing (RTA) of the wafer, and further affect uniformity of electric performances of resulting dies across the wafer.
Chinese patent application CN101454870A discloses a method providing uniform temperatures across a limited region of a wafer during a RTA process. The method includes: determining a first reflectivity in a first portion of the limited region by measuring a density of first structures in the first portion. Next, the method determines a second reflectivity in a second portion of the limited region by measuring a density of second structures in the second portion. Specifically, the first structures include diffusion fill shapes and polysilicon conductor fill shapes (non-active dummy structures); and, the second structures include active circuit structures. The first reflectivity and the second reflectivity are then compared. Following this, the method adjusts an amount of overlap between the diffusion fill shapes and the polysilicon conductor fill shapes of the first structures, to balance the first reflectivity and the second reflectivity.
The method described above adds fill shapes to a particular region during circuit layout design, to add dummy structures (dummy gates or dummy AAs) to a die, thereby balancing reflectivities against RTA radiation in regions of the wafer.
However, a problem lies in that dummy structures normally can not be added to some particular regions of some circuits, e.g., under inductors in RF circuits or under Metal-Insulator-Metal (MIM) capacitors, because dummy structures placed in these particular regions may affect electric performances of the circuits.